The present invention disclosed herein relates to a phase-locked loop, and more particularly, to a charge pump circuit improving current matching properties and a phase-locked loop including the charge pump circuit.
When a signal is shown as a frequency domain, the signal is divided into an amplitude component indicating intensity of the signal and a phase component indicating timing properties. The phase component of the signal is sensitive to a temperature or an effect of a peripheral circuit, a phase of the signal, that is, a frequency is easily changed. For example, in transmitting a digital signal, a clock signal is generated with a signal delay depending on a signal path. As the signal delay is generated, the phase of the signal is changed. Accordingly, since a beginning and an end of the clock signal become unclear, a circuit for synchronizing the beginning and the end of the clock signal is necessary.
A phase-locked loop (PLL) circuit is a frequency feedback circuit stably outputting a random frequency signal to be synchronized with a frequency of an external input signal. PLL circuits described above are generally used in analog and digital electronic circuit systems.
For example, PLL circuits are used to stably supply oscillating frequencies of local oscillation circuits in order to transmit and receive signals in wireless communication systems. Also, PPL circuits are used to generate reference clock signals necessary for processing digital signals in digital circuits such as microprocessors.
However, PPLs, depending on external environments, may vary in signal outputting properties. For example, according to external environments such as peripheral temperatures, power voltages, and process variations, outputting properties of PPLs vary. Particularly, PPLs vary in outputting properties with current matching properties of a charge pump (CP).